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CDCM6208V1FRGZR Datasheet(PDF) 58 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 58 Page - Texas Instruments

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1.05V
Outputs tristated
Step2
XO startup
Step3
Ref Clk Cntr
Step4
FBCLK Cntr
Step5
VCO CAL
Step6 : PLL lock time
Step1 : Pwr up
RESETN held low
From here
on Device
is locked
Device outputs held static low
( YxP=low, Yxn= high)
Y 4( HCSL)
Y4p
Y4n
1.8V
CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
Typical Applications (continued)
Table 35. Initialization Routine (continued)
STEP
DURATION
COMMENTS
This counter of 64 k clock cycles needs to expire before any further
power-up step is done inside the device. This counter ensures that
64k Reference clock cycles at
Step 3: Ref Clock Counter
the input to the PFD from PRI or SEC input has stabilized in
PFD input
frequency. The duration of this step can range from 640 µs (fPFD=
100 MHz) to 8 sec (8 kHz PFD).
64k FBCLK cycles with CW=32;
The duration is similar to Step 3,
The Feedback counter delays the startup by another 64k PFD clock
or can be more accurately
cycles. This is so that all counters are well initialized and also ensure
Step 4: FBCLK counter
estimated as:
additional timing margin for the reference clock to settle. This step
Approximately 64k x PS_A x
can range from 640 µs (fPFD= 100 MHz) to 8 sec (fPFD= 8kHz).
N/2.48 GHz
This step calibrates the VCO to the exact frequency range, and
Step 5: VCO calibration
128k PFD reference clock cycles
takes exactly 128k PFD clock cycles. The duration can therefore
range from 1280 µs (fPFD= 100 MHz) to 16 sec (f PFD= 8 KHz).
The Outputs turn on immediately after calibration. A small frequency
error remains for the duration of approximately 3 x LBW (so in
Step 6: PLL lock time
approximately 3 x LBW
synthesizer mode typically 10 µs). The initial output frequency will be
lower than the target output frequency, as the loop filter starts out
initially discharged.
The PLL lock indicator if selected on output STATUS0 or STATUS1
approximately 2305 PFD clock
Step 7: PLL Lock indicator high
will go high after approximately 2048 to 2560 PFD clock cycles to
cycles
indicate PLL is now locked.
Figure 42. Powerup Time
58
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


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