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CDCM6208V1FRGZR Datasheet(PDF) 53 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 53 Page - Texas Instruments

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Pico Cell Clocking
DPLL
CDCM6208
APLL
GPS receiver
IEEE1588
timing extract
Ethernet
SyncE
Et
he
rne
t
Timing
1pps
1pps
Core
Packet
network
FBADC
RXADC
TXDAC
RF LO
RF LO
CDCM6208
Synthesizer
Mode
TMS320TCI6616/18
DSP
AIF
ALT
CORE
SRIO
PCIe
Packet
Accel
DR
Base Band DSP
Clocking
CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The CDCM6208 is a highly integrated clock generator and jitter cleaner. The CDCM6208 derives its output
clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers.
11.2 Typical Applications
Figure 37. Typical Application Circuit
Figure 38. Typical Application Circuit
11.2.1 Design Requirements
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, a 10 GigEthernet). Fully estimating the clock jitter
impact on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR
bandwidth.
Copyright © 2015, Texas Instruments Incorporated
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