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CDCM6208V1FRGZR Datasheet(PDF) 5 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 5 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
Pin Functions (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
LVCMOS out
Output/I
LVCMOS in
SDO: SPI Serial Data AD0: I2C Address Offset Bit 0 inputPIN2: Control pin 2 in pin
SDO/AD0/PIN2
3
nput
LVCMOS in
mode
no pull resistor
LVCMOS no pull
SCS: SPI Latch EnableAD1: I2C Address Offset Bit 1 inputPIN3: Control pin 3 in pin
SCS/AD1/PIN 3
4
Input
resistor
mode
LVCMOS no pull
SCL/PIN4
5
Input
SCL: SPI/I2C ClockPIN4: Control pin 4 in pin mode
resistor
In SPI/I2C programming mode, external RESETN signal (active low).
RESETN = V IL: device in reset (registers values are retained)
RESETN = V IH: device active. The device can be programmed via SPI while
RESETN is held low (this is useful to avoid any false output frequencies at power
LVCMOS
RESETN/PWR
44
Input
up). (2)
w/ 50k
Ω pull-up
In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1
= 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not
possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3
V.
Regulator Capacitor; connect a 10 µF cap with ESR below 1
Ω to GND at
REG_CAP
40
Output
Analog
frequencies above 100 kHz
Power Down Active low. When PDN = VIH is normal operation. When PDN = VIL, the
device is disabled and current consumption minimized. Exiting power down resets
LVCMOS
PDN
43
Input
the entire device and defaults all registers. It is recommended to connect a capacitor
w/ 50k
Ω pull-up
to GND to hold the device in power-down until the digital and PLL related power
supplies are stable. See section on power down in the application section.
LVCMOS
Active low. Device outputs are synchronized on a low-to-high transition on the
SYNCN
42
Input
w/ 50k
Ω pull-up
SYNCN pin. SYNCN held low disables all outputs.
(2)
Note: the device cannot be programmed in I2C while RESETN is held low.
Copyright © 2015, Texas Instruments Incorporated
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