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CDCM6208V1FRGZR Datasheet(PDF) 49 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 49 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
Table 24. Register 13 (continued)
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
Output channel 5 8-b integer divider setting
11:4
OUTDIV5[7:0]
(Divider value is register value +1)
Output Channel 5
3:0
FRACDIV5[19:16]
Output channel 5 20-b fractional divider setting, bits 19-16
Table 25. Register 14
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:0
FRACDIV5[15:0]
Output Channel 5
Output channel 5 20-b fractional divider setting, bits 15-0
Table 26. Register 15
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
Output channel 6 fractional divider's 3-b pre-divider setting (this pre-
divider is bypassed if Q15.9 = 0)
000
→ Divide by 2
12:10
PRE_DIV_CH6[2:0]
001
→ Divide by 3
111
→ Divide by 1
All other combinations reserved
Output channel 6 fractional divider enable:
9
EN_FRACDIV_CH6
0
→ Disable
1
→ Enable
Output channel 6 LVCMOS output slew:
8
LVCMOS_SLEW_CH6
0
→ Normal
1
→ Slow
Output channel 6 negative-side LVCMOS enable:
0
→ Disable
7
EN_LVCMOS_N_CH6
1
→ Enable (Negative side can only be enabled if positive side is
enabled)
Output Channel 6
Output channel 6 positive-side LVCMOS enable:
6
EN_LVCMOS_P_CH6
0
→ Disable
1
→ Enable
5
RESERVED
This bit must be set to 0
Output channel 6 type selection:
00 or 01
→ LVDS
4:3
SEL_DRVR_CH6[1:0]
10
→ LVCMOS
11
→ HCSL
Output channel 6 enable:
00
→ Disable
2:1
EN_CH6[1:0]
01
→ Enable
10
→ Drive static 0
11
→ Drive static 1
Output channel 6 Supply Voltage Selection:
0
SUPPLY_CH6 (1)
0
→ 1.8 V
1
→ 2.5/3.3 V
(1)
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 27. Register 16
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
Copyright © 2015, Texas Instruments Incorporated
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