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CDCM6208V1FRGZR Datasheet(PDF) 47 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 47 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
Table 19. Register 8
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8
RESERVED
This bit must be set to 0
Output Channels 2
Output channels 2 and 3 8-b output integer divider setting
7:0
OUTDIV2_3[7:0]
and 3
(Divider value is register value +1)
Table 20. Register 9
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
Output MUX setting for output channel 4:
00 and 11
→ PLL
14:13
OUTMUX_CH4[1:0]
01
→ Primary input
10
→ Secondary input
Output channel 4 fractional divider's 3-b pre-divider setting (this pre-
divider is bypassed if Q9.9 = 0)
000
→ Divide by 2
12:10
PRE_DIV_CH4[2:0]
001
→ Divide by 3
111
→ Divide by 1
All other combinations reserved
Output channel 4 fractional divider enable:
9
EN_FRACDIV_CH4
0
→ Disable
1
→ Enable
Output channel 4 LVCMOS output slew:
8
LVCMOS_SLEW_CH4
0
→ Normal
1
→ Slow
Output channel 4 negative-side LVCMOS enable:
0
→ Disable
7
EN_LVCMOS_N_CH4
Output Channel 4
1
→ Enable (Negative side can only be enabled if positive side is
enabled)
Output channel 4 positive-side LVCMOS enable:
6
EN_LVCMOS_P_CH4
0
→ Disable
1
→ Enable
5
RESERVED
This bit must be set to 0
Output channel 4 type selection:
00 or 01
→ LVDS
4:3
SEL_DRVR_CH4[2:0]
10
→ LVCMOS
11
→ HCSL
Output channel 4 enable:
00
→ Disable
2:1
EN_CH4[1:0]
01
→ Enable
10
→ Drive static 0
11
→ Drive static 1
Output channel 4 Supply Voltage Selection:
0
SUPPLY_CH4 (1)
0
→ 1.8 V
1
→ 2.5/3.3 V
(1)
It is ok to power up the device with a 2.5 V / 3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 21. Register 10
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: CDCM6208V1F


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