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CDCM6208V1FRGZR Datasheet(PDF) 45 Page - Texas Instruments

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Part # CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 45 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
Table 15. Register 4 (continued)
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
Primary Input (R) Divider Selection:
11:8
CLK_PRI_DIV[3:0]
Primary Input Divider
0000
→ Divide by 1
1111
→ Divide by 16
Secondary Input Buffer Type Selection:
00
→ CML
7:6
SEC_SELBUF[1:0]
01
→ LVDS
10
→ LVCMOS
Secondary Input
11
→ Crystal
Secondary input enable:
5
EN_SEC_CLK
0
→ Disable
1
→ Enable
Primary Input Buffer Type Selection:
00
→ CML
4:3
PRI_SELBUF[1:0]
01
→ LVDS
10
→ LVCMOS
Primary Input
11
→ LVCMOS
Primary input enable:
2
EN_PRI_CLK
0
→ Disable
1
→ Enable
Supply voltage for secondary input:
1
SEC_SUPPLY (1)
Secondary Input
0
→ 1.8 V
1
→ 2.5/3.3 V
Supply voltage for primary input:
0
PRI_SUPPLY (2)
Primary Input
0
→ 1.8 V
1
→ 2.5/3.3 V
(1)
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_SEC supply voltage used.
(2)
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_PRI supply voltage used.
Table 16. Register 5
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
Output Channel 1 Type Selection:
00, 01
→ LVDS
8:7
SEL_DRVR_CH1[1:0]
10
→ CML
11
→ PECL
Output Channel 1
Output channel 1 enable:
00
→ Disable
6:5
EN _CH1[1:0]
01
→ Enable
10
→ Drive static 0
11
→ Drive static 1
Output Channel 0 Type Selection:
00, 01
→ LVDS
4:3
SEL_DRVR_CH0[1:0]
10
→ CML
11
→ PECL
Output Channel 0
Output channel 0 enable:
00
→ Disable
2:1
EN_CH0[1:0]
01
→ Enable
10
→ Drive static 0
11
→ Drive static 1
Copyright © 2015, Texas Instruments Incorporated
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