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CDCM6208V1FRGZR Datasheet(PDF) 44 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 44 Page - Texas Instruments

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CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
Table 14. Register 3
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:13
RESERVED
These bits must be set to 0
Reference clock status enable on Status 1 pin:
12
ST1_SEL_REFCLK
0
→ Disable
1
→ Enable (See Table 7 for full description)
Loss-of-reference Enable on Status 1 pin:
11
ST1_LOR_EN
0
→ Disable"
1
→ Enable (See Table 7 for full description)
PLL Lock Indication Enable on Status 1 pin:
10
ST1_PLLLOCK_EN
0
→ Disable
1
→ Enable (See Table 7 for full description)
Device Status
Reference clock status enable on Status 0 pin:
9
ST0_SEL_REFCLK
0
→ Disable
1
→ Enable (See Table 7 for full description)
Loss-of-reference Enable on Status 0 pin:
8
ST0_LOR_EN
0
→ Disable
1
→ Enable (See Table 7 for full description)
PLL Lock Indication Enable on Status 0 pin:"
7
ST0_PLLLOCK_EN
0
→ Disable
1
→ Enable (See Table 7 for full description)
Device Reset Selection:
6
RSTN
Device Reset
0
→ Device In Reset (retains register values)
1
→ Normal Operation
Output Channel Dividers Synchronization Enable:
5
SYNCN
Output Divider
0
→ Forces synchronization
1
→ Exits synchronization
PLL/VCO Calibration Enable:
4
ENCAL
PLL/VCO
0
→ Disable
1
→ Enable
PLL Prescaler 1 Integer Divider Selection:
00
→ Divide-by-4
01
→ Divide-by-5
3:2
PS_B[1:0]
PLL Prescaler Divider B
10
→ Divide-by-6
11
→ RESERVED
used for Y2, Y3, Y6, and Y7
PLL Prescaler 0 Integer Divider Selection:
00
→ Divide-by-4
01
→ Divide-by-5
1:0
PS_A[1:0]
PLL Prescaler Divider A
10
→ Divide-by-6
11
→ RESERVED
used in PLL feedback, Y0, Y1, Y4, and Y5
Table 15. Register 4
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
Smart MUX Pulse Width Selection. This bit controls the Smart MUX
delay and waveform reshaping.
00
→ PLL Smart MUX Clock Delay and Reshape Disabled (default
15:14
SMUX_PW[1:0]
in all pin modes)
01
→ PLL Smart MUX Clock Delay Enable
10
→ PLL Smart MUX Clock Reshape Enable
11
→ PLL Smart MUX Clock Delay and Reshape Enable
Smart MUX Mode Selection:
Reference Input Smart
0
→ Auto select
MUX
13
SMUX_MODE_SEL
1
→ Manual select
Note: in Auto select mode, both input buffers must be enabled. Set
R4.5 = 1 and R4.2 = 1
Smart MUX Selection for PLL Reference:
0
→ Primary
12
SMUX_REF_SEL
1
→ Secondary (only if REF_SEL pin is high)
This bit is ignored when smartmux is set to auto select (e.g. R4.13 =
0). See Table 7 for details.
44
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


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