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CDCM6208V1FRGZR Datasheet(PDF) 40 Page - Texas Instruments

Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 40 Page - Texas Instruments

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CDCM6208
CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
Programming (continued)
In an I2C bus system, the CDCM6208V1F acts as a slave device and is connected to the serial bus (data bus
SDA and clock bus SCL). The SDA port is bidirectional and uses an open drain driver to permit multiple devices
to be connected to the same serial bus. The CDCM6208V1F allows up to four unique CDCM6208V1F slave
devices to occupy the I2C bus in addition to any other I2C slave device with a different I2C address. These slave
devices are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a
matching slave address responds to subsequent I2C commands. The device slave address is 10101xx (the two
LSBs are determined by the AD1 and AD0 pins). The five MSBs are hard-wired, while the two LSBs are set
through pins on device powerup.
Figure 33.
During the data transfer through the I2C port interface, one clock pulse is generated for each data bit transferred.
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data
line can change only when the clock signal on the SCL line is low. The start data transfer condition is
characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is
characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are
always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed
by an acknowledge bit and bytes are sent MSB first.
The acknowledge bit (A) or non-acknowledge bit (A) is the 9thbit attached to any 8-bit data byte and is always
generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A
= 1). A = 0 is done by pulling the SDA line low during the 9thclock pulse and A = 1 is done by leaving the SDA
line high during the 9thclock pulse.
The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave
devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line
(consisting of the 7-bit slave address (MSB first) and an R/W bit), the device whose address corresponds to the
transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the
selected device waits for data transfer with the master. The CDCM6208V1F slave address bytes are given in
below table.
After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop
condition to end data transfer during the 10 thclock pulse following the acknowledge bit for the last data byte from
the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during
the 9thclock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave
knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the
low period before the 10 thclock pulse, and high during the 10 thclock pulse to assert a stop condition.
40
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