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CDCM6208V1FRGZR Datasheet(PDF) 4 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 4 Page - Texas Instruments

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CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
Pin Functions (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference
LVCMOS
selection is also controlled through Register 4 bit 12.REF_SEL = 0 (
≤ VIL): selects
REF_SEL
6
Input
w/ 50k
Ω pull-up
PRI_REFREF_SEL = 1 (
≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See
Table 36 for detail.
ELF
41
Output
Analog
External loop filter pin for PLL
Y0_P
14
Output
Universal
Output 0 Positive Terminal
Y0_N
15
Output
Universal
Output 0 Negative Terminal
Y1_P
17
Output
Universal
Output 1 Positive Terminal
Y1_N
16
Output
Universal
Output 1 Negative Terminal
VDD_Y0_Y1 (2
13,
PWR
Analog
Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V
pins)
18
Y2_P
20
Output
Universal
Output 2 Positive Terminal
Y2_N
21
Output
Universal
Output 2 Negative Terminal
Y3_P
23
Output
Universal
Output 3 Positive Terminal
Y3_N
22
Output
Universal
Output 3 Negative Terminal
VDD_Y2_Y3 (2
19,
PWR
Analog
Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V
pins)
24
Y4_P
26
Output
Universal
Output 4 Positive Terminal
Y4_N
25
Output
Universal
Output 4 Negative Terminal
VDD_Y4
27
PWR
Analog
Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V
Y5_P
29
Output
Universal
Output 5 Positive Terminal
Y5_N
28
Output
Universal
Output 5 Negative Terminal
VDD_Y5
30
PWR
Analog
Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V
Y6_P
32
Output
Universal
Output 6 Positive Terminal
Y6_N
33
Output
Universal
Output 6 Negative Terminal
VDD_Y6
31
PWR
Analog
Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V
Y7_P
35
Output
Universal
Output 7 Positive Terminal
Y7_N
36
Output
Universal
Output 7 Negative Terminal
VDD_Y7
34
PWR
Analog
Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V
Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The
VDD_VCO
39
PWR
Analog
supply of this pin and the VDD_PLL2 supply pin can be combined as they are both
analog and sensitive supplies;
VDD_PLL1
37
PWR
Analog
Analog Power Supply Connections
Analog Power Supply Connections; This pin is sensitive to power supply noise; The
VDD_PLL2
38
PWR
Analog
supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both
power-sensitive, analog supply pins
Digital Power Supply Connections; This is also the reference supply voltage for all
DVDD
48
PWR
Analog
control inputs and must match the expected input signal swing of control inputs.
GND
PAD
PWR
Analog
Power Supply Ground and Thermal Pad
STATUS0
46
Output
LVCMOS
Status pin 0 (see Table 7 for details)
Output
LVCMOS
STATUS1: Status pin in SPI/I2C modes. For details see Table 6 for pin modes and
STATUS1/PIN0
45
and
no pull resistor
Table 7 for status mode. PIN0: Control pin 0 in pin mode.
Input
Serial Interface Mode or Pin mode selection.SI_MODE[1:0]=00: SPI
LVCMOSw
SI_MODE1
47
Input
mode;SI_MODE[1:0]=01: I2C mode;SI_MODE[1:0]=10: Pin Mode (No serial
50k
Ω pull-up
programming);SI_MODE[1:0]=11: RESERVED
LVCMOSw
SI_MODE0
1
50k
Ω pull-down
LVCMOS in
Open drain out
SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write bi-directional), open
SDI/SDA/PIN1
2
I/O
LVCMOS in
drain output; requires a pull-up resistor in I2C mode;PIN1: Control pin 1 in pin mode
no pull resistor
4
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


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