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CDCM6208V1FRGZR Datasheet(PDF) 39 Page - Texas Instruments

Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 39 Page - Texas Instruments

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SCS
SCL
SCI
WRITE
READ
SCI
SCO
HI-Z
16-BIT COMMAND
16-BIT DATA
'21¶7&$5(
A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
CDCM6208
SDO
(#34)
Data out
SCS (#37)
LVCMOS
&
0
0
0
SDO internal
enable signal
CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
Programming (continued)
10.5.2 Reading from the CDCM6208V1F
As with the write operation, the host first initiates a SPI transfer by asserting the SCS pin low. The host signals a
read operation by shifting a logical high in the first bit position, signaling the CDCM6208V1F that the host is
imitating a read data transfer from the device. During the portion of the message in which the host specifies the
CDCM6208V1F register address, the host presents this information on the SDI pin of the device (for the first 15
clock cycles after the W/R bit). During the 16 clock cycles that follow, the CDCM6208V1F presents the data from
the register specified in the first half of the message on the SDO pin. The SDO output is 3-stated anytime SCS is
high, so that multiple SPI slave devices can be connected to the same serial bus. The host signals the
CDCM6208V1F that the transfer is complete by de-asserting the SCS pin high.
Figure 31.
10.5.3 Block Write/Read Operation
The device supports a block write and block read operation. The host need only specify the lowest address of the
sequence of addresses that the host needs to access. The CDCM6208V1F will automatically increment the
internal register address pointer if the SCS pin remains low after the SPI port finishes the initial 32-bit
transmission sequence. Each transmission of 16 bits (a data payload width) results in the device automatically
incrementing the address pointer (provided the SCS pin remains active low for all sequences).
Figure 32. CDCM6208V1F SPI Port Message Sequencing
10.5.4 I2C Serial Interface
With SI_MODE1=0 and SI_MODE0=1 the CDCM6208V1F enters I 2C mode. The I2C port on the CDCM6208V1F
works as a slave device and supports both the 100 kHz standard mode and 400 kHz fast mode operations. Fast
mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses
of less than 50 ns duration. The inputs of the device also incorporates a Schmitt trigger at the SDA and SCL
inputs to provide receiver input hysteresis for increased noise robustness.
NOTE
Communication through I2C is not possible while RESETN is held low.
Copyright © 2015, Texas Instruments Incorporated
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