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CDCM6208V1FRGZR Datasheet(PDF) 37 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 37 Page - Texas Instruments

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OSC
=
OUT
(O × PS_A)
f
f
SEC_REF
VCO
=
M
(N × PS_A)
f
f
PRI_REF
VCO
=
(M × R)
(N × PS_A)
f
f
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
0
0
0
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Fixed (4 bits)
Register Address (11 bits)
Data Payload (16 bits)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Message Field Definition
Bit Definition
Order of Transmission
First Out
Examples:
Read Register 4:
1|000 0|000 0000 0100| xxxx xxxx xxxx xxxx
Write 0xF0F1 to Register 5:
0|000 0|000 0000 0101| 1111 0000 1111 0001
MSB
LSB
CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
10.4.5.2 SPI - Serial Peripheral Interface
To enable the SPI port, tie the communication select pins SI_MODE[1:0] to ground. SPI is a master/slave
protocol in which the host system is always the master; therefore, the host always initiates communication
to/from the device. The SPI interface consists of four signal pins. The device SPI address is 0000.
Table 8. Serial Port Signals in SPI Mode
PIN
I/O
DESCRIPTION
NAME
NUMBER
SDI/SDA/PIN1
2
Input
SDI: SPI Serial Data Input
SDO/AD0/PIN2
3
Output
SDO: SPI Serial Data
SCS/AD1/PIN3
4
Input
SCS: SPI Latch Enable
SCL/PIN4
5
Input
SCL: SPI/I2C Clock
The host must present data to the device MSB first. A message includes a transfer direction bit, an address field,
and a data field as depicted in Figure 30
Figure 30. CDCM6208V1F SPI Message Format
10.4.5.2.1
Configuring the PLL
The CDCM6208V1F allows configuring the PLL to accommodate various input and output frequencies either
through an I2C or SPI programming interface or in the absence of programming, the PLL can be configured
through control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop
Filter, Feedback Divider, Prescaler Divider, and Output Dividers.
For the PLL to operate in closed loop mode, the following condition in Equation 2 has to be met when using
primary input for the reference clock, and the condition in Equation 3 has to be met when using secondary input
for the reference clock.
(2)
(3)
In Equation 2 and Equation 3, ƒPRI_REF is the reference input frequency on the primary input and ƒSEC_REF is the
reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the
feedback divider, and PS_A the prescaler divider A.
The output frequency, ƒOUT, is a function of ƒVCO, the prescaler A, and the output divider (O), and is given by
Equation 4. (Use PS_B in for outputs 2, 3, 6, and 7).
(4)
Copyright © 2015, Texas Instruments Incorporated
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