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CDCM6208V1FRGZR Datasheet(PDF) 34 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 34 Page - Texas Instruments

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CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
Table 6. CDCM6208V1F Loop Filter Recommendation for Pin Mode (continued)
Internal LPF
PRI_REF
SEC_REF
Components
Recommended
f(PFD)
ICP
Use Case
Loop Filter
(MHz)
(mA)
Freq
Freq
R3
C3
C1/R2/C2
Type
Type
(MHz)
(MHz)
(Ohm)
(pF)
MAN-
100
10
0x17
24-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x18
25-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x19
26-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x1A
27-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x1B
28-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x1C
29-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x1D
30-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x1E
31-V1F
25
LVCMOS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
MAN-
100
10
0x1F
32-V1F
25
LVDS
25
Crystal
25
2.5m
100pF/500Ohm/22nF
242.5
SEC
Ohm
10.4.3 Status Pins Definition
The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by
reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization
of which vitals are mapped to these two pins. Table 7 lists the three events that can be mapped to each status
pin and which can also be read in the register space.
Table 7. CDCM6208V1F Status Pin Definition List
STATUS
REGISTER BIT
SIGNAL TYPE
SIGNAL NAME
DESCRIPTION
SIGNAL NAME
NO.
SEL_REF
LVCMOS
STATUS0, 1
Reg 3.12
Indicates Reference Selected for PLL:
Reg 3.9
0
→ Primary input selected to drive PLL
1
→ Secondary input selected to drive PLL
LOS_REF
LVCMOS
STATUS0, 1
Reg 3.11
Loss of selected reference input observed at active input:
Reg 3.8
0
→ Reference input present
1
→ Loss of reference input
Important Note 1: For LOS_REF to operate properly, the secondary
input SEC_IN must be enabled. Set register Q4.5=1. If register
Q4.5 is set to zero, LOS_REF will output a static high signal
regardless of the actual input signal status on PRI_IN.
PLL_UNLOCK
LVCMOS
STATUS0, 1
Reg 3.10
Indicates unlock status for PLL (digital):
Reg 3.7
PLL locked
→ Q21.02 = 0 and VSTATUS0/1= VIH
PLL unlocked
→ Q21.2 = 1 and VSTATUS0/1= VILSee note
(1)
Note 2: I f the smartmux is enabled and both reference clocks stall,
the STATUSx output signal will 98% of the time indicate the LOS
condition with a static high signal. However, in 2% of the cases, the
LOS detection engine erroneously stalls at a state where the
STATUSx output PLL lock indicator will signalize high for 511 out of
every 512 PFD clock cycles.
(1)
The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1.
34
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


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