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CDCM6208V1FRGZR Datasheet(PDF) 31 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 31 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
Table 5. Pre-Configured Settings of CDCM6208V1F Accessible by PIN[4:0](1) (2)
Type
Type2
f(PFD)
f(VCO)
SPI
MAN-
0
I/O
25
Disable
25
Crystal
25
2500
125
PECL
125
PECL
125
PECL
125
PECL
25
HCSL
100
HCSL
100
Disable
100
Disable
Default
SEC
I2C
MAN-
1
I/O
25
Disable
25
Crystal
25
2500
125
PECL
125
PECL
125
PECL
125
PECL
25
HCSL
100
HCSL
100
Disable
100
Disable
Default
SEC
Reserv
11
ed
LVCM
MAN-
10
0x00
1-V1F
25
25
Crystal
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
OS
SEC
LVCM
MAN-
10
0x01
2-V1F
25
25
Crystal
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
25
LVDS
25
LVDS
25
LVDS
25
LVDS
OS
SEC
LVCM
MAN-
LVCM
LVCM
10
0x02
3-V1F
25
25
Crystal
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
25
LVDS
25
LVDS
25
25
OS
SEC
OS-PN
OS-PN
LVCM
MAN-
LVCM
10
0x03
4-V1F
25
25
Crystal
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
156.25
LVDS
156.25
LVDS
25
LVDS
125
OS
SEC
OS-PN
LVCM
MAN-
LVCM
LVCM
10
0x04
5-V1F
25
25
Crystal
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
25
LVDS
25
LVDS
125
125
OS
SEC
OS-PN
OS-PN
LVCM
MAN-
10
0x05
6-V1F
25
25
Crystal
25
2500
100
PECL
100
PECL
156.25
PECL
156.25
PECL
25
LVDS
100
HCSL
156.25
LVDS
156.25
LVDS
OS
SEC
LVCM
MAN-
LVCM
10
0x06
7-V1F
25
25
Crystal
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
156.25
LVDS
156.25
LVDS
25
LVDS
OS
SEC
OS-PN
LVCM
MAN-
LVCM
10
0x07
8-V1F
25
25
Crystal
25
2500
156.25
PECL
156.25
PECL
25
PECL
25
PECL
125
156.25
LVDS
100
HCSL
100
HCSL
OS
SEC
OS-PN
LVCM
MAN-
10
0x08
9-V1F
25
25
Crystal
25
2500
156.25
PECL
156.25
PECL
100
PECL
100
PECL
156.25
LVDS
156.25
LVDS
100
HCSL
100
HCSL
OS
SEC
LVCM
MAN-
10
0x09
10-V1F
25
25
Crystal
25
2500
100
PECL
100
PECL
156.25
CML
156.25
CML
25
LVDS
100
HCSL
156.25
LVDS
156.25
LVDS
OS
SEC
12.000
LVCM
MAN-
LVCM
LVCM
LVCM
LVCM
10
0x0A
11-V1F
25
25
Crystal
25
2500
100
PECL
100
PECL
100
PECL
100
PECL
25
125
50
000183
OS
SEC
OS-PN
OS-PN
OS-PN
OS-PN
1055
LVCM
MAN-
LVCM
LVCM
LVCM
10
0x0B
12-V1F
25
25
Crystal
25
2400
25
PECL
25
PECL
100
CML
100
CML
25
25
100
HCSL
12
OS
SEC
OS-PN
OS-PN
OS-PN
LVCM
MAN-
LVCM
LVCM
10
0x0C
13-V1F
25
25
Crystal
25
2500
156.25
PECL
156.25
PECL
125
PECL
125
PECL
25
25
25
LVDS
100
HCSL
OS
SEC
OS-PN
OS-PN
66.666
LVCM
MAN-
LVCM
10
0x0D
14-V1F
25
25
Crystal
25
2500
25
PECL
25
PECL
156.25
PECL
156.25
PECL
100
HCSL
100
HCSL
156.25
LVDS
666666
OS
SEC
OS-PN
6667
33.333
LVCM
MAN-
LVCM
10
0x0E
15-V1F
25
25
Crystal
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
25
LVDS
25
LVDS
25
LVDS
333333
OS
SEC
OS-PN
3333
(1)
The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable.
(2)
The REF_SEL input pin selects the primary or secondary input in MANUAL mode. That is: If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The
primary and secondary input stage power supply must be always connected.
For all pin modes, STATUS0 outputs the PLL_LOCK signal and STATUS1 the LOSS OF REFERENCE.
General Note: in all pin mode, all voltage supplies must either be 1.8 V or 2.5/3.3 V and the PWR pin number 44 must be set to 0 or 1 accordingly. In SPI and I2C mode, the supply
voltages can be "mixed and matched" as long as the corresponding register bits reflect the supply voltage setting for each desired 1.8 V or 2.5/3.3 V supply. Exception: inputs configured
for LVDS signaling (Type = LVDS) are supply agnostic, and therefore can be powered from 2.5 V/3.3 V or 1.8 V regardless of the supply select setting of pin number 44.
Copyright © 2015, Texas Instruments Incorporated
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