CDCM6208V1FRGZR datasheet(3/87 Pages) TI1 | 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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Y7_N

Y7_P

VDD_Y7

Y6_N

Y6_P

VDD_Y6

VDD_Y5

36

35

34

33

28

27

26

29

25

30

31

32

SDI/SDA/PIN1

SDO/AD0/PIN2

SCS/AD1/PIN3

REF_SEL

SCL/PIN4

1

2

3

4

5

6

7

8

9

10

11

12

Y5_P

PRI_REFN

PRI_REFP

SI_MODE0

Y4_N

SEC_REFP

SEC_REFN

Y4_P

VDD_Y4

Y5_N

DVDD

VDD

VDD_Y2_Y3

VDD_PRI_REF

VDD_SEC_REF

_Y0_Y1

CDCM6208V1F

www.ti.com

SCAS943 – MAY 2015

6 Description (continued)

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp

(unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k - 40 MHz) on outputs using

fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output

using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The

CDCM6208V1F is packaged in a small 48-pin 7 mm x 7 mm QFN package.

7 Pin Configuration and Functions

RGZ Package

48 Pin VQFN

Top View

Pin Functions

I/O

TYPE

DESCRIPTION

NAME

NO.

PRI_REFP

8

Input

Universal

Primary Reference Input +

PRI_REFN

9

Input

Universal

Primary Reference Input –

Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to

VDD_PRI_REF

7

PWR

Analog

VDD_SEC_REF.

SEC_REFP

11

Input

Universal

Secondary Reference Input +

SEC_REFN

12

Input

Universal

Secondary Reference Input –

Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to

VDD_SEC_REF

10

PWR

Analog

VDD_PRI_REF(1).

(1)

If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.

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CDCM6208V1FRGZR Datasheet(PDF) 3 Page - Texas Instruments

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