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CDCM6208V1FRGZR Datasheet(PDF) 29 Page - Texas Instruments

Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 29 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
10.3 Feature Description
Phase Noise: The Phase Noise performance of the device can be summarized to:
Table 2. Synthesizer Mode (Loop filter BW >250 kHz)
RANDOM JITTER (ALL OUTPUTS)
TOTAL JITTER
TYPICAL
MAXIMUM
MAXIMUM
Integer divider
Fractional divider
10k-20MHz
12k-20MHz
10k-100MHz
DJ-unbound
DJ 10k-40MHz
RJ 10k-20MHz
RJ 10k-20MHz
0.27 ps-rms (Integer division)
50-220 ps-pp,
0.3 ps-rms (int div)(1)
0.625 ps-rms (int div)
20 ps-pp (2)
0.7ps-rms (fractional div)
see Figure 4
(1)
Integrated Phase Noise (12kHz - 20 MHz) for 156.25 MHz output clock measured at room temperature using a 25 MHz Low Noise
reference source
(2)
TJ = 20 pspp applies for LVPECL, CML, and LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over
PVT.
Table 3. Jitter Cleaner Mode (Loop filter BW < 1 kHz)
RANDOM JITTER (ALL OUTPUTS)
TOTAL JITTER
TYPICAL
MAXIMUM
MAXIMUM
Integer divider
Fractional divider
10k-20MHz
10k-20MHz
10k-100MHz
DJ unbound
DJ 10k-40MHz
RJ 10k-20MHz
RJ 10k-20MHz
1.6 ps-rms (Integer division)
70-240 ps-pp,
2.1 ps-rms (int div)
2.14 ps-rms (int div)
40 ps-pp
2.3 ps-rms (fractional div) 10k-20MHz
see Figure 4
Spurious Performance: The spurious performance is as follows:
Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.
Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential
signaling level operated at 122.88 MHz output frequency in the Nyquist range.
Device outputs:
The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML),
low-swing CML (LVDS like), HCSL, and LVCMOS signaling.
Table 4. Device Outputs
FREQUENCY
Outputs
LVPECL
CML
LVDS
HCSL
LVCMOS
OUTPUT DIVIDER
RANGE
Y[3:0]
X
X
X
Integer only
1.55 - 800 MHz
Integer
1.55 - 800 MHz
Y[7:4]
X
X
X
Fractional
1.00 - 400 MHz
Outputs [Y0:Y3] are driven by 8-b continuous integer dividers per pair. Outputs [Y4:Y7] are each driven by 20-b
fractional dividers that can achieve any frequency with better than 1ppm frequency accuracy. The output skew is
typically less than 40 ps for differential outputs. The LVCMOS outputs support adjustable slew rate control to
control EMI. Pairs of 2 outputs can be operated at 1.8 V, 2.5 V or 3.3 V power supply voltage.
Device Configuration:32 distinct pin modes are available that cover many common use cases without the need
for any serial programming of the device. For maximum flexibility the device also supports SPI and I2C
programming. I2C offers 4 distinct addresses to support up to 4 devices on the same programming lines.
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: CDCM6208V1F


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