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CDCM6208V1FRGZR Datasheet(PDF) 28 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 28 Page - Texas Instruments

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Control
Output
PLL
Input
N
8-b,10-b
R
4-b
Host
Interface
Status/
Monitoring
Power
Conditioning
CDCM6208
Differential/
LVCMOS
Differential
LVCMOS/
XTAL
LVPECL/
CML/
LVDS
LVDS/
LVCMOS/
HCSL
Fractional Div
M
14-b
Integer Div
LVDS/
LVCMOS/
HCSL
VCO
:
(2.39-2.55) GHz
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
PRI REF
_
SEC REF
_
Integer Div
PreScaler PS_A
÷4, ÷5, ÷6
ELF
REF_SEL
Fractional Div
20-b
20-b
8-b
8-b
Fractional Div
20-b
Fractional Div
20-b
PreScaler PS_B
÷4, ÷5, ÷6
Φ
CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
10 Detailed Description
10.1 Overview
Supply Voltage: The CDCM6208V1F supply is internally regulated. Therefore each core and I/O supply can be
mixed and matched in any order according to the application needs. The device jitter performance is independent
of supply voltage.
Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and
VCO that operates from 2.39 GHz to 2.55 GHz.
Reference inputs: The primary and secondary reference inputs support differential and single ended signals from
8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. There is a 4-
bit reference divider available on the primary reference input. The input mux between the two references
supports simply switching or can be configured as Smart MUX and supports glitchless input switching.
Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the
output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent
prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then
be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an
output MUX. A total of 2 output MUXes are available.
Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz. The
charge pump gain is programmable and the loop filter consists of internal + partially external passive
components and supports bandwidths from a few Hz up to 400kHz.
10.2 Functional Block Diagram
Figure 26. High-Level Block Diagram of CDCM6208V1F
28
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCM6208V1F


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