CDCM6208V1FRGZR datasheet(21/87 Pages) TI1 | 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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(spur/20)

-12

p-p

CLK

2 x 10

Deterministic Jitter (ps

) =

x 10

x f

p

CDCM6208V1F

www.ti.com

SCAS943 – MAY 2015

8.24.1 Fractional Output Divider Jitter Performance

The fractional output divider jitter performance is a function of the fraction output divider input frequency as well

as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least

number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 4, the

largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in

the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a

time window of 200 ms. The RJ impact on TJ is estimated for a BERT 10

(–12) – 1. This measurement result is

overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW

limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

See Figure 8 for reference.

Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify

design and cost, the CDCM6208V1F has built in internal voltage regulation, improving the power supply noise

rejection over designs with no regulators. As a result, the following output rejection is achieved:

The DJ due to PSRR can be estimated using Equation 1:

(1)

Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the

according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.

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