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CDCM6208V1FRGZR Datasheet(PDF) 18 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 18 Page - Texas Instruments

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background image
SCL
SCS
SDO
t4
t
5
t2
t3
t 7
t
6
t1
SDI
t8
A31
D0
D1
D15
D1
D0
A30
'21¶7&$5(
'21¶7&$5(
tri-state
CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
8.22 I
2C TIMING(1)
PARAMETER
STANDARD MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
fSCL
SCL Clock Frequency
0
100
0
400
kHz
tsu(START)
START Setup Time (SCL high before SDA low)
4.7
0.6
μs
th(START)
START Hold Time (SCL low after SDA low)
4.0
0.6
μs
tw(SCLL)
SCL Low-pulse duration
4.7
1.3
μs
tw(SCLH)
SCL High-pulse duration
4.0
0.6
μs
th(SDA)
SDA Hold Time (SDA valid after SCL low)
0 (2)
3.45
0
0.9
μs
tsu(SDA)
SDA Setup Time
250
100
ns
tr-in
SCL / SDA input rise time
1000
300
ns
tf-in
SCL / SDA input fall time
300
300
ns
tf-out
SDA Output fall time from VIH min to VIL max with a bus
250
250
ns
capacitance from 10 pF to 400 pF
tsu(STOP)
STOP Setup Time
4.0
0.6
μs
tBUS
Bus free time between a STOP and START condition
4.7
1.3
μs
tglitch_filter
Pulse width of spikes suppressed by the input glitch filter
75
300
75
300
ns
(1)
For additional information, refer to the I2C-Bus specification, Version 2.1 (January 2000); the CDCM6208V1F meets the switching
characteristics for standard mode and fast mode transfer.
(2)
The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge
of SCL.
Figure 2. CDCM6208V1F SPI Port Timing
18
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Product Folder Links: CDCM6208V1F


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