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CDCM6208V1FRGZR Datasheet(PDF) 15 Page - Texas Instruments

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Part No. CDCM6208V1FRGZR
Description  2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V1FRGZR Datasheet(HTML) 15 Page - Texas Instruments

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CDCM6208V1F
www.ti.com
SCAS943 – MAY 2015
8.19 Output Skew and Sync to Output Propagation Delay Characteristics
VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PS_A = 4
9
10.5
11
1/fPS_A
Propagation delay SYNCN
↑ to output
tPD-PS
f VCO = 2.5 GHz
PS_A = 5
9
10.2
11
1/fPS_A
toggling high
PS_A = 6
9
10.0
11
1/fPS_A
Part-to-Part Propagation delay
ΔtPD-PS
variation SYNCN
↑ to output toggling
Fixed supply voltage, temp, and device setting(1)
0
1
1/f PS_A
high(1)
OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
tSK,LVDS
Skew between Y[7:4] LVDS
Y[7:4] = LVDS
40
ps
tSK,LVDS
Skew between Y[3:0] LVDS
Y[3:0] = LVDS
40
ps
tSK,LVDS
Skew between Y[7:0] LVDS
Y[7:0] = LVDS
80
ps
tSK,CML
Skew between Y[3:0] CML
Y[3:0] = CML
40
ps
tSK,PECL
Skew between Y[3:0] PECL
Y[3:0] = LVPECL
40
ps
tSK,HCSL
Skew between Y[7:4] HCSL
Y[7:4] = HCSL
40
ps
tSK,SE
Skew between Y[7:4] CMOS
Y[7:4] = CMOS
50
ps
OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
Skew between Y[7:4] LVDS and
tSK,CMOS-LVDS
Y[4] = CMOS, Y[7:5] = LVDS
2.5
ns
CMOS mixed
Skew between Y[7:0] CMOS and
tSK,CMOS-PECL
Y[7:4] = CMOS, Y[3:0] = LVPECL
2.5
ns
LVPECL mixed
Skew between Y[3:0] LVPECL and
tSK,PECL-LVDS
Y[0] = LVPECL, Y[3:1] = LVDS
120
ps
LVDS mixed
Skew between Y[3:0] LVPECL and
tSK,PECL-CML
Y[0] = LVPECL, Y[3:1] = CML
40
ps
CML mixed
Skew between Y[7:0] LVDS and
tSK,LVDS-PECL
Y[7:4] = LVDS, Y[3:0] = LVPECL
180
ps
LVPECL mixed
Skew between Y[7:4] LVDS and
tSK,LVDS-HCSL
Y[4] = LVDS, Y[7:5] = HCSL
250
ps
HCSL mixed
OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125
Skew between Y[7:4] LVDS using all
tSK,DIFF, frac
fractional divider with the same
Y[7:4] = LVDS
200
ps
divider setting
(1)
SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: CDCM6208V1F


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