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CDCE62005 Datasheet(PDF) 9 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 9 Page - Texas Instruments

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CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
Electrical Characteristics (continued)
recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
LVDS OUTPUT(1)(2)
fclk
Output frequency (see Figure 8)
Configuration Load
0
800
MHz
|VOD|
Differential output voltage
RL = 100 Ω
270
550
mV
ΔVOD
LVDS VOD magnitude change
50
mV
Offset Voltage
40°C to 85°C
1.24
V
ΔVOS
VOS magnitude change
40
mV
Short circuit Vout+ to ground
VOUT = 0
27
mA
Short circuit Vout– to ground
VOUT = 0
27
mA
Outputs are set to 491.52 MHz
Reference (PRI_REF or SEC_REF)
tpho
1.65
ns
to output phase offset
Reference at 30.72 MHz
tpd(LH)/tpd( Propagation delay from PRI_REF
Crosspoint to Crosspoint, Bypass
3.1
ns
HL)
or SEC_REF to outputs
Mode
tsk(o)
(3)
Skew, output to output For Y0 to Y4 All Outputs set at 200 MHz
25
ps
CO
Output capacitance on Y0 to Y4
VCC = 3.3 V; VO = 0 V or VCC
5
pF
IOPDH
Power down output current
VO = VCC
25
μA
IOPDL
Power down output current
VO = 0 V
5
μA
Duty cycle
45%
55%
tr / tf
Rise and fall time
20% to 80% of VOUT(PP)
110
160
190
ps
LVCMOS-TO-LVDS(4)
VCC/2 to Crosspoint. Output are at the
Output skew between LVCMOS
tskP_c
same output frequency and use the
0.9
1.4
1.9
ns
and LVDS outputs
same output divider configuration.
LVPECL OUTPUT
Output frequency, Configuration
fclk
0
1500
MHz
load (see Figure 9 and Figure 10)
LVPECL high-level output voltage
VOH
VCC –1.06
VCC –0.88
V
load
LVPECL low-level output voltage
VOL
VCC–2.02
VCC–1.58
V
load
|VOD|
Differential output voltage
610
970
mV
Outputs are set to 491.52 MHz,
tpho
Reference to Output Phase offset
1.47
ns
Reference at 30.72 MHz
tpd(LH)/
Propagation delay from PRI_REF
Crosspoint to Crosspoint, Bypass
3.4
ns
or SEC_REF to outputs
Mode
tpd(HL)
tsk(o)
Skew, output to output For Y0 to Y4 All Outputs set at 200 MHz
25
ps
CO
Output capacitance on Y0 to Y4
VCC = 3.3 V; VO = 0 V or VCC
5
pF
IOPDH
VO = VCC
25
μA
Power Down output current
IOPDL
VO = 0 V
5
μA
Duty Cycle
45%
55%
tr / tf
Rise and fall time
20% to 80% of VOUT(PP)
55
75
135
ps
(2)
The phase of LVCMOS is lagging in reference to the phase of LVDS.
(3)
The tsk(o) specification is only valid for equal loading of all outputs.
(4)
All typical values are at VCC = 3.3 V, temperature = 25°C
Copyright © 2008–2015, Texas Instruments Incorporated
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