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CDCE62005 Datasheet(PDF) 6 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
Download  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 6 Page - Texas Instruments

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CDCE62005
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage range(2)
–0.5
4.6
V
VI
Input voltage range(3)
–0.5
VCC + 0.5
V
VO
Output voltage range(3)
–0.5
VCC + 0.5
V
Input Current (VI < 0, VI > VCC)
±20
mA
Output current for LVPECL/LVCMOS Outputs (0 < VO < VCC)
±50
mA
TJ
Maximum junction temperature
125
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2)
All supply voltages have to be supplied simultaneously.
(3)
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
2000
pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
750
JESD22-C101, all pins(2)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
(1) (2)
RGZ
THERMAL METRIC(3)
UNIT
48 PINS
28.9(4)
20.4(5)
RθJA
Junction-to-ambient thermal resistance
27.3(6)
20.3(7)
RθJC(top)
Junction-to-case (top) thermal resistance
12.9
RθJB
Junction-to-board thermal resistance
4.0
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
2(4)
2(5)
θJP
Junction-to-Pad(8)
2(6)
2(7)
(1)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(2)
Connected to GND with 36 thermal vias (0,3 mm diameter).
(3)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(4)
JEDEC Compliant Board (6X6 VIAs on PAD), Ariflow = 0 LFM
(5)
JEDEC Compliant Board (6X6 VIAs on PAD) , Airflow = 100 LFM
(6)
Recommended Layout (7X7 VIAs on PAD), Airflow = 0 LFM
(7)
Recommended Layout (7X7 VIAs on PAD), Airflow = 100 LFM
(8)
θJP (Junction – Pad) is used for the QFN Package, because the main heat flow is from the Junction to the GND-Pad of the QFN.
6
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