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CDCE62005 Datasheet(PDF) 5 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 5 Page - Texas Instruments

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CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
Pin Functions(1) (continued)
PIN
TYPE
DESCRIPTION
NAME
NUMBER
SPI_CLK
LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The
24
I
input has an internal 150-k
Ω pull-up resistor if left unconnected it will default to logic level
1.
SPI_MOSI
LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the
23
I
SPI bus interface. The input has an internal 150-k
Ω pull-up resistor if left unconnected it
will default to logic level 1.
TEST_MODE
33
I
This pin should be tied high or left unconnected.
REF_SEL
If Auto Reference Select Mode is OFF this Pin acts as External Input Reference Select
Pin;
The REF_SEL signal selects one of the two input clocks:
31
I
REF_SEL [1]: PRI_REF is selected; REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-k
Ω pull-up resistor if left unconnected it will default to logic
level 1. If Auto Reference Select Mode in ON (for example, EECLKSEL bit -- Register 5
Bit 5 -- is 1 ), then REF_SEL pin input setting is ignored.
Power_Down
Active Low. Power down mode can be activated via this pin. See Table 4 for more details.
The input has an internal 150-k
Ω pull-up resistor if left unconnected it will default to logic
12
I
level 1. SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load
the EEPROM.
SYNC
Active Low. Sync mode can be activated via this pin. See Table 4 for more details. The
14
I
input has an internal 150-k
Ω, pull-up resistor if left unconnected it will default to logic level
1.
AUX IN
Auxiliary Input is a single ended input including an on-board oscillator circuit so that a
43
I
crystal may be connected.
AUX OUT
Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by
13
O
Output 2 or Output 3.
PRI_REF+
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary
45
I
Reference Clock.
PRI_REF–
Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock.
46
I
In case of LVCMOS input on PRI_REF+, connect this pin through 1 k
Ω resistor to GND.
SEC_REF+
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary
3
I
Reference Clock.
SEC_REF–
Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference
2
I
Clock. In case of LVCMOS input on SEC_REF+, connect this pin through 1 k
Ω resistor to
GND.
TESTOUTA
30
Analog
Reserved. Pull Down to GND Via a 1-k
Ω Resistor.
REG_CAP1
4
Analog
Capacitor for the internal Regulator. Connect to a 10uF Capacitor (X5R or X7R)
REG_CAP2
38
Analog
Capacitor for the internal Regulator. Connect to a 10uF Capacitor (X5R or X7R)
VBB
48
Analog
Capacitor for the internal termination Voltage. Connect to a 1uF Capacitor (X5R or X7R)
EXT_LFP
40
Analog
External Loop Filter Input Positive
EXT_LFN
41
Analog
External Loop Filter Input Negative.
PLL_LOCK
37
O
Output that indicates PLL Lock Status. See Figure 31.
U0P:U0N
27, 28
The Main outputs of CDCE62005 are user definable and can be any combination of up to
5 LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are
U1P:U1N
19, 20
selectable via SPI interface. The power-up setting is EEPROM configurable.
U2P:U2N
16,17
O
U3P:U3N
9, 10
U4P:U4N
6, 7
Copyright © 2008–2015, Texas Instruments Incorporated
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