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SI53314 Datasheet(PDF) 4 Page - Silicon Laboratories |
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SI53314 Datasheet(HTML) 4 Page - Silicon Laboratories |
4 / 32 page Si53314 4 Rev. 1.0 Table 3. DC Common Characteristics (VDD =1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current IDD —65 100 mA Output Buffer Supply Current (Per Clock Output) @100 MHz (diff) @200 MHz (CMOS) IDDOX LVPECL (3.3 V) — 35 — mA Low Power LVPECL (3.3 V)* — 35 — mA LVDS (3.3 V) — 20 — mA CML (3.3 V) — 35 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (1.8 V, SFOUT = Open/0), per output, CL =5pF, 200MHz —5— mA CMOS (2.5 V, SFOUT = Open/0), per output, CL =5pF, 200MHz —8— mA CMOS (3.3 V, SFOUT = 0/1), per output, CL =5pF, 200MHz —15— mA Input Clock Voltage Reference VREF VREF pin IREF = +/-500 A — VDD/2 — V Input High Voltage VIH SFOUTx, CLK_SEL, OEx 0.8 x VDD —— V Input Mid Voltage VIM SFOUTx, 3-level input pins 0.45 x VDD 0.5 x VDD 0.55 x VDD V Input Low Voltage VIL SFOUTx, CLK_SEL, OEx — — 0.2 x VDD V Internal Pull-down Resistor RDOWN CLK_SEL, SFOUTx — 25 — k Internal Pull-up Resistor RUP OEx, SFOUTx — 25 — k *Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power. |
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