EVAL-SDP-CB1Z datasheet(61/90 Pages) AD

Part #	EVAL-SDP-CB1Z

Description	4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference

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Data Sheet

AD7124-4

Rev. A | Page 61 of 90

Figure 109. Simultaneous 50 Hz and 60 Hz Rejection

POST FILTERS

The post filters provide rejection of 50 Hz and 60 Hz

simultaneously and allow the user to trade off settling time and

rejection. These filters can operate up to 27.27 SPS or can reject

up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These

filters are realized by post filtering the output of the sinc3 filter.

The filter bits must be set to all 1s to enable the post filter. The post

filter option to use is selected using the POST_FILTER bits in the

filter register. In Figure 110, the blocks shown in gray are unused.

Figure 110. Post Filters

Table 61 shows the output data rates with the accompanying

settling times and the rejection.

When continuously converting on a single channel, the first

conversion requires a time of tSETTLE. Subsequent conversions

occur at 1/fADC. When multiple channels are enabled (either

manually or using the sequencer), the settling time is required

to generate a valid conversion on each enabled channel.

Table 61. AD7124-4 Post Filters: Output Data Rate, Settling Time (tSETTLE), and Rejection

Output Data

Rate (SPS)

f3dB

(Hz)

tSETTLE, Full Power

Mode (ms)

tSETTLE, Mid Power

Mode (ms)

tSETTLE, Low Power

Mode (ms)

Simultaneous Rejection of 50 Hz ± 1 Hz

and 60 Hz ± 1 Hz (dB)1

27.27

17.28

38.498

38.998

39.662

47

25

15.12

41.831

42.331

42.995

62

20

13.38

51.831

52.331

52.995

86

16.67

12.66

61.831

62.331

62.995

92

1

Stable master clock used.

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

30

60

90

120

150

FREQUENCY (Hz)

SINC3/SINC4

FILTER

MODULATOR

AVERAGING

BLOCK

POST

FILTER

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