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SI5380-EVB Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI5380-EVB Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 50 page 3.3.1 Input Configuration and Terminations Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be DC-cou- pled. Unused inputs can be disabled and left unconnected when not in use. Standard AC-coupled Single-ended 100 Standard AC-coupled Differential LVPECL 3.3 V, 2.5 V LVPECL INx INxb INx 50 50 50 Si5380 Si5380 Pulsed CMOS Standard Standard Pulsed CMOS 50 100 Standard AC-coupled Differential LVDS INx 3.3 V, 2.5 V LVDS or CML 50 Si5380 Pulsed CMOS Standard INxb INxb INxb 3.3 V, 2.5 V, 1.8 V LVCMOS Pulsed CMOS DC-coupled Single-ended 3.3 V, 2.5 V, 1.8 V LVCMOS INx Pulsed CMOS Standard Si5380 50 R 2 R1 VDD R1 (Ω) R2 (Ω) 1.8V 549 442 2.5V 680 324 3.3V 750 243 Resistor values for fIN_PULSED < 1 MHz Figure 3.5. Termination of Differential and LVCMOS Input Signals 3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN) Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a clock input. Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins IN_SEL[1:0] Selected Input Zero Delay Mode Disabled Zero Delay Mode Enabled 0 0 IN0 IN0 0 1 IN1 IN1 1 0 IN2 IN2 1 1 IN3 Reserved Si5380 Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 0.96 | 8 |
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