SI5380 datasheet(32/50 Pages) SILABS

Part #	SI5380

Description	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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Manufacturer	SILABS [Silicon Laboratories]

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Parameter

Symbol

Min

Typ

Max

Unit

SCLK Rise and Fall Time

Tr/Tf

—

10

ns

SCLK Period

TC

50

—

ns

Delay Time, SCLK Fall to SDO

Active

TD1

—

12.5

ns

Delay Time, SCLK Fall to SDO

TD2

—

12.5

ns

Delay Time, CSb Rise to SDO

Tri-State

TD3

—

12.5

ns

Setup Time, CSb to SCLK

TSU1

25

—

ns

Hold Time, SCLK Fall to CSb

TH1

25

—

ns

Setup Time, SDI to SCLK Rise

TSU2

12.5

—

ns

Hold Time, SDI to SCLK Rise

TH2

12.5

—

ns

Delay Time Between Chip Selects

(CSb)

TCS

1.9

—

Tc

SCLK

CSb

SDI

SDO

TSU1

TD1

TSU2

TD2

TC

TCS

TD3

TH2

TH1

Figure 5.2. 4-Wire SPI Serial Interface Timing

Table 5.11. SPI Timing Specifications (3-Wire)

Parameter

Symbol

Min

Typ

Max

Unit

SCLK Frequency

fSPI

—

20

MHz

SCLK Duty Cycle

TDC

40

—

60

%

SCLK Rise and Fall Time

Tr/Tf

—

10

ns

SCLK Period

TC

50

—

ns

Delay Time, SCLK Fall to SDIO Turn-on

TD1

—

12.5

ns

Delay Time, SCLK Fall to SDIO Next-bit

TD2

—

12.5

ns

Delay Time, CSb Rise to SDIO Tri-State

TD3

—

12.5

ns

Setup Time, CSb to SCLK

TSU1

25

—

ns

Hold Time, SCLK Fall to CSb

TH1

25

—

ns

Si5380 Data Sheet

Electrical Specifications

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Rev. 0.96 | 31

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