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SI5380 Datasheet(PDF) 14 Page - Silicon Laboratories

Part # SI5380
Description  Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

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3.4.6 LOL Detection
A loss of lock (LOL) monitor asserts the LOL bit when the DSPLL has lost synchronization with the selected input clock. There is also a
dedicated active-low LOLb pin which reflects the loss of lock condition. The LOL monitor measures the frequency difference between
the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set)
and another that clears the indicator (LOL Clear). A block diagram of the LOL monitor is shown in the figure below. The live LOL regis-
ter always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current
state of the LOL monitor.
LOL
DSPLL
LPF
PD
÷M
LOL
Si5380
÷5
LOL
Clear
LOL
Set
Timer
Feedback
Clock
fIN
Reset
Set
Q
RS Latch
Live
Sticky
LOL
LOLb
LOL Monitor
Figure 3.11. LOL Status Indicators
Each of the frequency monitors have adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. Having two sepa-
rate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indica-
ted when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more
than 2 ppm frequency difference is shown in the figure below.
Phase Detector Frequency Difference (ppm)
Hysteresis
LOL
LOCKED
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
0
Lost Lock
20000
0.2
2
Figure 3.12. LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely phase lock to
the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisi-
tion. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calcula-
ted using the ClockBuilder Pro utility.
Si5380 Data Sheet
Functional Description
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.96 | 13


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