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SI5369C-C-GQ Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI5369C-C-GQ Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 84 page Si5369 Rev. 1.0 5 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current1,6 IDD LVPECL Format 622.08 MHz Out All CKOUTs Enabled — 394 435 mA LVPECL Format 622.08 MHz Out 1 CKOUT Enabled — 253 284 mA CMOS Format 19.44 MHz Out All CKOUTs Enabled — 278 400 mA CMOS Format 19.44 MHz Out 1 CKOUT Enabled — 229 261 mA Disable Mode — 165 — mA CKINn Input Pins2 Input Common Mode Voltage (Input Thresh- old Voltage) VICM 1.8 V ± 5% 0.9 — 1.4 V 2.5 V ± 10% 1 — 1.7 V 3.3 V ± 10% 1.1 — 1.95 V Input Resistance CKNRIN Single-ended 20 40 60 k Single-Ended Input Voltage Swing (See Absolute Specs) VISE fCKIN <212.5 MHz See Figure 1. 0.2 — — VPP fCKIN >212.5 MHz See Figure 1. 0.25 — — VPP Differential Input Voltage Swing (See Absolute Specs) VID fCKIN <212.5 MHz See Figure 1. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 1. 0.25 — — VPP Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. |
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