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LMX2582RHAT Datasheet(PDF) 8 Page - Texas Instruments |
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LMX2582RHAT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 40 page LSB MSB ttCSt ttCHt tCES ttCWLt ttCWHt ttESt tEWH DATA CLK LE LMX2582 SNAS680A – DECEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Figure 1. Serial Data Input Timing Diagram There are several considerations for programming: • A slew rate of at least 30 V/µs is recommended for the CLK, DATA, LE • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter • The LE pin may be held high after programming and clock pulses will be ignored • The CLK signal should not be high when LE transitions to low • When CLK and DATA lines are shared between devices, it is recommended to divide down the voltage to the CLK, DATA and LE pins closer to the minimum voltage. This provides better noise immunity • If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2582 |
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