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54ACT563 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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54ACT563 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 6 page Connection Diagrams Functional Description The ’ACT563 contains eight D-type latches with TRI-STATE complementary outputs. When the Latch Enable (LE) input is HIGH, data on the D n inputs enters the latches. In this con- dition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran- sition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with enter- ing new data into the latches. Function Table Inputs Internal Outputs Function OE LE D Q O H X X X Z High-Z H H L H Z High-Z H H H L Z High-Z H L X NC Z Latched L H L H H Transparent L H H L L Transparent L L X NC NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Pin Assignment for DIP and Flatpak DS100331-3 Pin Assignment for LCC DS100331-4 DS100331-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 |
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