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AN611 Datasheet(PDF) 1 Page - Silicon Laboratories

Part No. AN611
Description  USING THE ISOVOLT DC/DC CONVERTER REFERENCE DESIGN
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Maker  SILABS [Silicon Laboratories]
Homepage  http://www.silabs.com
Logo SILABS - Silicon Laboratories

AN611 Datasheet(HTML) 1 Page - Silicon Laboratories

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Rev. 0.2 9/11
Copyright © 2011 by Silicon Laboratories
AN611
AN611
USING THE ISOVOLT DC/DC CONVERTER
REFERENCE DESIGN
1. Design Overview
The ISOvolt isolated dc/dc reference design shown in Figure 1 is a low-cost, robust, isolated dc/dc converter
capable of delivering a maximum of 3 W of output power. This isolated power converter enables Silicon Labs’
isolation products to be powered from a single bias supply, eliminating the need for separate supplies on both sides
of the isolation device. This design features fold-back current limiting and thermal shutdown protection, low EMI
operation, and high (78%) operating efficiency. Input voltage ranges are 3.3 or 4.5 Vdc to 5.5 Vdc and generate
isolated output voltages of 3.3, 5.0, 7.0, or 24 V, depending on the transformer and output regulator used. Referring
to Figure 1, the ISOvolt reference design is based on push-pull switching topology. The timing generator is a
CT600-PX0624GM MCU, which has been factory-programmed to generate primary-side transformer switch timing.
Figure 1. ISOvolt Isolated DC/DC Block Diagram
This MCU has a maximum bias voltage of 3.3 V, allowing applications having 2.7 V < VIN < 3.3 V dc. Higher values
of VIN require the addition of input regulator (U2). The timing generator outputs are conditioned by high and low-
side gate driver circuits, which drive the switches on transformer T1's primary at a frequency of 500 kHz. The
resulting ac voltage on the secondary-side is rectified by a full-wave Schottky diode circuit and filtered by a bulk
capacitor (C10). An active clamp circuit sinks current during light output loads (50 mA or less) to ensure the dc
voltage stays below the maximum input voltage value of the linear output regulator. The resulting conditioned dc
voltage is regulated by a linear output regulator (U4).
The ISOvolt reference design board (see Figure 4) also contains digital isolator U3 (Silicon Labs’ Si864IBC with
three forward channels and one reverse channel) for customer use. The combination of ISOvolt and the onboard
isolator is useful in applications, such as isolated serial ports. The user can connect external signals to input blocks
J1 and J2, and VOUT+ supplies bias to the output side of the isolator.
Note: U3 maximum VDD2 is 5.5 V. If VDD2 exceeds 5 V, the value of resistor R6 must be increased to ensure that U3 pin 16
does not exceed 5.5 V under any operating conditions. For BOM, schematic, and layout details, see the “Discrete ISO-
volt Isolated DC-DC Converter Reference Design Users Guide”.
U1
C8051T600‐GM
VDD
GND
5
3
11
C3
0.1uF
Ceramic
C1
10uF
1
C2
0.1
U2
VSS
VIN
VOUT 2
3
1
 XC6215P
3,2
VIN+
(P1)
VIN‐
(P2)
P0.3
C6 
470pF
 NPO
R6
220
VIN+
2
3
1
Q4
R3
1.0K
C7 
470pF
 NPO
3
2
1
Q5
R1
200K
TP12
/RST
8
R4
1.0
TP3
R11
200K
1
2
3
TP5
Q6
4
6
C4 
470pF
 NPO
R9
220
VIN+
2
3
1
Q1
R2
1.0K
C5 
470pF
 NPO
3
2
1
Q2
R7
200K
R10
1.0
TP8
R5
200K
1
2
3
Q3
P0.4
TP6
TP11 R12
0.0
C8 
NOPOP
C14
X7R
4.7uF
R17
100K
J3
3.3V
VDD1
GND1
A1
A2
A3
A4
U3
Si8641BB
VDD2
GND2
B1
B2
B3
B4
C13
1uF
R13*
R14
R15
R16
VIN+
VOUT+
*R12‐R15 = 100
2
1
3
4
5
GND1
6
EN/NC
7
8
15
16
14
13
12
11
10
9
GND2
EN/NC2
7Vdc 
MAX
C10
10uF
u4
C11
X5R
10uF
VOUT+
(P3)
VSS
VIN
VOUT
D1
D2
T1
XFMR
XC6220B
2
5
1
CE
3
8
7,6
5
VOUT‐
(P4)
R19
100
R20
10K
R18
8.25K
D3
Q8
J1
J2
R6
0.0
C12
1uF
Low‐Side Driver
High‐Side Driver
Rectifiers and Active Clamp
Output Regulator
Digital Isolator
Timing Generator
Input Regulator
TP14
TP13


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