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EFM32LG880 Datasheet(PDF) 51 Page - Silicon Laboratories |
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EFM32LG880 Datasheet(HTML) 51 Page - Silicon Laboratories |
51 / 85 page ...the world's most energy friendly microcontrollers 2014-06-13 - EFM32LG880FXX - d0117_Rev1.30 51 www.silabs.com Figure 3.40. EBI Read Enable Related Output Timing EBI_BL[1:0] RDSETUP (0, 1, 2, ...) EBI_A[27:0] EBI_BL EBI_A EBI_AD[15:8] ADDR[7:0] EBI_CSn EBI_AD[7:0] EBI_REn RDSTRB (1, 2, 3, ...) RDHOLD (0, 1, 2, ...) t SU_REn t SU_REn t SU_REn t SU_REn t WIDTH_REn Z Z t H_REn t H_REn t H_REn t H_REn Z Z Z DATA[7:0] Table 3.22. EBI Read Enable Related Output Timing Symbol Parameter Min Typ Max Unit tOH_REn 1 2 3 4 Output hold time, from trailing EBI_REn/ EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid -10.00 + (RDHOLD * tHFCORECLK) ns tOSU_REn 1 2 3 4 5 Output setup time, from EBI_AD, EBI_A, EBI_CSn, EBI_BLn valid to leading EBI_REn/EBI_NANDREn edge -10.00 + (RDSETUP * tHFCORECLK) ns tWIDTH_REn 1 2 3 4 5 6 EBI_REn pulse width -9.00 + ((RD- STRB+1) * tHFCORE- CLK) ns 1Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing modes D8A24ALE and D16A16ALE) 2Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn) 3Applies for all polarities (figure only shows active low signals) 4Measurement done at 10% and 90% of V DD (figure shows 50% of VDD) 5The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length of tOSU_REn by 1/2 * tHFCLKNODIV. 6When page mode is used, RDSTRB is replaced by RDPA for page hits. |
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