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XC164CS Datasheet(PDF) 60 Page - Infineon Technologies AG

Part No. XC164CS
Description  16-Bit Single-Chip Microcontroller
Download  71 Pages
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Maker  INFINEON [Infineon Technologies AG]
Homepage  http://www.infineon.com
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XC164CS Datasheet(HTML) 60 Page - Infineon Technologies AG

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XC164
Derivatives
Timing Parameters
Data Sheet
56
V2.1, 2003-06
5
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC164 is controlled by the internal master clock
fMC.
The master clock signal
fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
fMC.
This influence must be regarded when calculating the timings for the XC164.
Figure 15
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
fCPU. The CPU clock can have the
same frequency as the master clock (
fCPU = fMC) or can be the master clock divided by
two:
fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
fSYS which has the same
frequency as the CPU clock signal
fCPU.
TCM
TCM
fMC
fOSC
fMC
fOSC
Phase Locked Loop Operation (1:N)
Direct Clock Drive (1:1)
TCM
fMC
fOSC
Prescaler Operation (N:1)


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