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XC164CS Datasheet(PDF) 32 Page - Infineon Technologies AG |
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XC164CS Datasheet(HTML) 32 Page - Infineon Technologies AG |
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32 / 71 page  XC164 Derivatives Functional Description Data Sheet 28 V2.1, 2003-06 3.7 The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one independent 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions (deadtime control). The compare channel can generate a single PWM output signal and is further used to modulate the capture/compare output signals. In capture mode the contents of compare timer T12 is stored in the capture registers upon a signal transition at pins CCx. Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked by the prescaled system clock. Figure 6 CAPCOM6 Block Diagram For motor control applications both subunits may generate versatile multichannel PWM signals which are basically either controlled by compare timer T12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). CC Channel 0 CC60 CC Channel 1 CC61 CC Channel 2 CC62 MCB04109 Offset Register T12OF Compare Timer T12 16-Bit Period Register T12P Mode Select Register CC6MSEL Trap Register Port Control Logic Cntrol Register CTCON Compare Register CMP13 Compare Timer T13 10-Bit Period Register T13P Block Commutation Control CC6MCON.H CC60 COUT60 CC61 COUT61 CC62 COUT62 CTRAP CC6POS0 CC6POS1 CC6POS2 f CPU f CPU COUT63 The timer registers (T12, T13) are not directly accessible. The period and offset registers are loading a value into the timer registers. |
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