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TPA3118D2QDAPRQ1 Datasheet(PDF) 4 Page - Texas Instruments

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Part # TPA3118D2QDAPRQ1
Description  100-W and 50-W Class-D Stereo Automotive Amplifiers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPA3118D2QDAPRQ1 Datasheet(HTML) 4 Page - Texas Instruments

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TPA3116D2-Q1, TPA3118D2-Q1
SLOS862A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
Table 1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AM[2:0]
13–15
I
AM avoidance frequency selection
AVCC
17
P
Analog supply
BSNL
20
BST
Bootstrap for negative left channel output, connect to 220-nF X5R, or better ceramic cap to OUTPL
BSNR
26
BST
Bootstrap for negative right channel output, connect to 220-nF X5R, or better ceramic cap to OUTNR
BSPL
24
BST
Bootstrap for positive left channel output, connect to 220-nF X5R, or better ceramic cap to OUTNL
BSPR
30
BST
Bootstrap for positive right channel output, connect to 220-nF X5R or better ceramic cap to OUTPR
FAULT
3
DO
General fault reporting including overtemperature, dc detect, open drain.
FAULT = High, normal operation
FAULT = Low, fault condition
GAIN/SLV
8
I
Selects gain and selects between master and slave modes depending on pin voltage divider.
GND
9, 22,
G
Ground
25, 28
GVDD
7
PO
Internally generated gate voltage supply. Not to be used as a supply or connected to any component
other than a 1-µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
LINN
11
I
Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
LINP
10
I
Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
MODSEL
1
I
Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance
to AVCC.
MUTE
12
I
Mute signal for fast disable or enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL
logic levels with compliance to AVCC.
OUTNL
21
PO
Negative left-channel output
OUTNR
27
PO
Negative right-channel output
OUTPL
23
PO
Positive left-channel output
OUTPR
29
PO
Positive right-channel output
PLIMIT
6
I
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect
directly to GVDD for no power limit.
PVCC
18, 19,
P
Power supply
31, 32
RINN
5
I
Negative audio input for right channel. Biased at 3 V.
RINP
4
I
Positive audio input for right channel. Biased at 3 V.
SD
2
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
SYNC
16
DIO
Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV pin.
Thermal pad
G
Connect to GND for best system performance. If not connected to GND, leave floating.
(1)
TYPE: DO = Digital output, I = Analog input, G = General ground, PO = Power output, BST = Bootstrap.
4
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPA3116D2-Q1 TPA3118D2-Q1


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