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PCM2704CDBR Datasheet(PDF) 11 Page - Texas Instruments |
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PCM2704CDBR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 47 page  PCM2704C, PCM2705C, PCM2706C, PCM2707C www.ti.com SBFS036B – MAY 2015 – REVISED AUGUST 2015 7.7 Audio Interface Timing Characteristics Load capacitance of LRCK, BCK, and DOUT is 20 pF. For timing diagrams, see Figure 1 and Figure 2. MIN MAX UNIT t(BCY) BCK pulse cycle time 300 ns t(BCH) BCK pulse duration, high 100 ns t(BCL) BCK pulse duration, low 100 ns t(BL) LRCK delay time from BCK falling edge –20 40 ns t(BD) DOUT delay time from BCK falling edge –20 40 ns t(LD) DOUT delay time from LRCK edge –20 40 ns t(DS) DIN setup time 20 ns t(DH) DIN hold time 20 ns 7.8 Audio Clock Timing Characteristics Load capacitance is 20 pF. For timing diagrams, see Figure 3. MIN MAX UNIT t(SLL), t(SLH) LRCK delay time from SYSCK rising edge –5 10 ns t(SBL), t(SBH) BCK delay time from SYSCK rising edge –5 10 ns 7.9 External ROM Read Interface Timing Characteristics For timing diagrams, see Figure 4. MIN MAX UNIT ƒ(CK) CK clock frequency 100 kHz t(BUF) Bus free time between a STOP and a START condition 4.7 μs t(LOW) Low period of the CK clock 4.7 μs t(HI) High period of the CK clock 4 μs t(RS-SU) Setup time for START/repeated START condition 4.7 μs t(S-HD) Hold time for START/repeated START condition 4 μs t(RS-HD) t(D-SU) Data setup time 250 ns t(D-HD) Data hold time 0 900 ns t(CK-R) Rise time of CK signal 20 + 0.1 CB 1000 ns t(CK-F) Fall time of CK signal 20 + 0.1 CB 1000 ns t(DT-R) Rise time of DT signal 20 + 0.1 CB 1000 ns t(DT-F) Fall time of DT signal 20 + 0.1 CB 1000 ns t(P-SU) Setup time for STOP condition 4 μs CB Capacitive load for DT and CK lines 400 pF VNH Noise margin at high level for each connected device (including hysteresis) 0.2 VDD V Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: PCM2704C PCM2705C PCM2706C PCM2707C |
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