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TLV320AIC3106 Datasheet(PDF) 10 Page - Texas Instruments |
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TLV320AIC3106 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 105 page TLV320AIC3106 SLAS509F – DECEMBER 2006 – REVISED DECEMBER 2014 www.ti.com 9.6 Timing Requirements: Audio Data Serial Interface (1) IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX I2S/LJF/RJF Timing in Master Mode td(WS) ADWS/WCLK delay time 50 15 ns td(DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns DSP Timing in Master Mode td(WS) ADWS/WCLK delay time 50 15 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns I2S/LJF/RJF Timing in Slave Mode tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 6 ns th(WS) ADWS/WCLK hold time 10 6 ns td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) 50 35 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns DSP Timing in Slave Mode tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 8 ns th(WS) ADWS/WCLK hold time 10 8 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns (1) All timing specifications are measured at characterization but not tested at final test. 10 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: TLV320AIC3106 |
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