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PCM1753DBQR Datasheet(PDF) 7 Page - Texas Instruments |
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PCM1753DBQR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 38 page ML MC MD t (MDS) t (MCY) t (MDH) t (MCH) t (MLS) t (MCL) LSB t (MLH) t (MHH) S 3 256 f ´ (1) seconds (min); fS: sampling rate. PCM1753, PCM1754, PCM1755 www.ti.com SLES092D – APRIL 2010 – REVISED AUGUST 2015 7.8 Control Interface Timing Requirements These timing parameters are critical for proper control port operation. MIN NOM MAX UNIT t(MCY) MC pulse cycle time 100 ns t(MCL) MC low-level time 50 ns t(MCH) MC high-level time 50 ns t(MCH) ML high-level time See (1) ns See Figure 1. t(MLS) ML falling edge to MC rising edge 20 ns t(MLH) ML hold time(2) 20 ns t(MDH) MD hold time 15 ns t(MCS) MD setup time 20 ns (2) MC rising edge for LSB to ML rising edge. Figure 1. Control Interface Timing Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: PCM1753 PCM1754 PCM1755 |
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