LMP92064

www.ti.com

SNOSCX0A – JUNE 2013 – REVISED DECEMBER 2014

7.3.2 Current Sense Input Channel Common-Mode and Differential Voltage Range (Dynamic Range

Considerations)

The input voltage should be in the range of –0.2 V to 2 V. The input can withstand voltage up to VDD + 0.3 V

absolute maximum but the operational range is limited to 2 V. Operation below –0.2 V or above 2 V on either

input pin will introduce severe gain errors and nonlinearity.

The maximum differential voltage (defined as the voltage difference between INCP and INCN) for which the part

is designed to work is 75 mV. Larger differential or common mode input voltages will not damage the part (as

long as the input pins remain between GND – 0.3 V and VDD + 0.3 V), however, exposure for extended periods

may affect device reliability. The ADC output code will not roll over and will clip at minimum or maximum scale

when the maximum differential voltage is exceeded.

7.3.3 Voltage Sense Input Channel

The voltage sensing channel of the LMP92064 has a high impedance buffer amplifier followed by a 12-bit

analog-to-digital converter. The binary code result of a conversion is also stored as a right-justified 16-bit number

as shown in Table 2, where the 4 most significant bits are always 0.

The output data of the voltage sense channel is accessible on registers 0x0201 and 0x0200.

Table 2. Ideal Voltage Channel Input Voltages and Output Codes

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT

Full scale range

BINARY CODE

HEX CODE

[B15:B0]

Least significant bit (LSB)

Maximum Positive Input

0000 1111 1111 1111

0x0FFF

Voltage

Zero Code Voltage

0 V

0000 0000 0000 0000

0x0000

7.3.4 Reference

The LMP92064 includes an internal 2.048-V band-gap reference for the ADCs, which eliminates the need of an

external reference and reduces component count and board space. The REFC pin is provided to allow bypassing

this internal reference for low noise operation. A 1-µF ceramic decoupling capacitor is required between the

REFC and REFG pins of the converter. The capacitor should be placed as close as possible to the pins of the

device.

7.3.5 Reset

There are two methods to reset the LMP92064. A soft reset is done by setting bit7=1 in the CONFIG_A register.

In a soft reset, the SPI state machine and the contents of registers 0x0000 and 0x0001 are unaffected.

A hardware reset is done by connecting the RESET pin of the LMP92064 to VDIG. If the pin is driven by a switch

or a GPIO, TI recommends adding an external RC filter to prevent reset glitches.

7.3.6 Device Power-Up Sequence

The sources providing power to the analog and digital supply pins of the LMP92064, VDD and VDIG, must ramp

up at the same time to have a proper power-on reset (POR) event. The easiest way to achieve it is to tie VDD

and VDIG to the same power source using a star configuration.

7.4 Device Functional Modes

7.4.1 ADC Operation

The LMP92064 includes two 12-bit ADCs that are continuously running in the background. The device is

configured, and data is read, using a four-wire SPI interface: CSB, SCLK, SDO and SDI. The device outputs its

data on SDO, and the data for both channels is synchronized such that all data read would be from the same

instant in time. New conversion data for both channels will only be made available after all registers are read in

descending sequential order (addresses 0x0203-0x0200). All registers must be read otherwise new conversion

data will not be available. Three different output data formats are available as detailed in Figure 20, Figure 21

and Figure 22.

Copyright © 2013–2014, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Links: LMP92064