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LMV762MAX Datasheet(PDF) 15 Page - Texas Instruments |
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LMV762MAX Datasheet(HTML) 15 Page - Texas Instruments |
15 / 25 page VREF C1 GND V+ SD OUT +IN -IN GND VIN R1 R2 LMV761, LMV762, LMV762Q-Q1 www.ti.com SNOS998I – FEBRUARY 2002 – REVISED OCTOBER 2015 9 Power Supply Recommendations To minimize supply noise, power supplies must be decoupled by a 0.1- μF ceramic capacitor in parallel with a 10- μF capacitor. Due to the nanosecond edges on the output transition, peak supply currents will be drawn during output transitions. Peak current depends on the capacitive loading on the output. The output transition can cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power supply to ring due to trace inductance and low self-resonance frequency of high ESR bypass capacitors. Treat the LMV6x as a high-speed device. Keep the ground paths short and place small (low-ESR ceramic) bypass capacitors directly between the V+ and V– pins. Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent current. 10 Layout 10.1 Layout Guidelines The LMV76x is designed to be stable and oscillation free, but it is still important to include the proper bypass capacitors and ground pick-ups. Ceramic 0.1- μF capacitors must be placed at both supplies to provide clean switching. Minimize the length of signal traces to reduce stray capacitance. 10.2 Layout Example Figure 26. Comparator With Hysteresis Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LMV761 LMV762 LMV762Q-Q1 |
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