Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY37384P256-83BGC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY37384P256-83BGC
Description  5V, 3.3V, ISR??High-Performance CPLDs
Download  62 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY37384P256-83BGC Datasheet(HTML) 7 Page - Cypress Semiconductor

Back Button CY37384P256-83BGC Datasheet HTML 3Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 4Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 5Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 6Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 7Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 8Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 9Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 10Page - Cypress Semiconductor CY37384P256-83BGC Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 62 page
background image
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 7 of 62
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used. Figure
5 illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input set-
up time to the output macrocells for any input is 3.5 ns and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
The Ultra37000 features:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable
timing model ensures compliance with the PCI AC specifica-
tions independent of the design.
Figure 4. Input/Clock Macrocell
0
1
2
3
O
C10C11
TO PIM
D
Q
D
Q
D
Q
LE
INPUT/CLOCK PIN
0
1
2
O
FROM CLOCK
CLOCK PINS
0
1
O
C12
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO CLOCK MUX
IN EACH
3
0
1
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
POLARITY INPUT
LOGIC BLOCK
C8 C9
C13, C14, C15
OR C16
O
Figure 5. Timing Model for CY37128
COMBINATORIAL SIGNAL
REGISTERED SIGNAL
D,T,L
O
CLOCK
INPUT
INPUT
OUTPUT
OUTPUT
tS = 3.5 ns
tCO = 4.5 ns
tPD = 6.5 ns


Similar Part No. - CY37384P256-83BGC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY37384P256-83BGC CYPRESS-CY37384P256-83BGC Datasheet
1Mb / 64P
   5V, 3.3V, ISRTM High-Performance CPLDs
More results

Similar Description - CY37384P256-83BGC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
ULTRA37000 CYPRESS-ULTRA37000 Datasheet
1Mb / 63P
   5V, 3.3V, ISR??High-Performance CPLDs
CY37000 CYPRESS-CY37000 Datasheet
1Mb / 67P
   5V, 3.3V, ISR High-Performance CPLDs
ULTRA37000 CYPRESS-ULTRA37000_04 Datasheet
2Mb / 64P
   5V, 3.3V, ISR High-Performance CPLDs
CY37256P160-125UMB CYPRESS-CY37256P160-125UMB Datasheet
2Mb / 64P
   5V, 3.3V, ISR??High-Performance CPLDs
CY37512VP400-83BBXC CYPRESS-CY37512VP400-83BBXC Datasheet
1Mb / 64P
   5V, 3.3V, ISRTM High-Performance CPLDs
logo
Micrel Semiconductor
SY89423V MICREL-SY89423V_07 Datasheet
80Kb / 8P
   5V/3.3V DUAL HIGH-PERFORMANCE
logo
Texas Instruments
PT8000 TI-PT8000 Datasheet
422Kb / 8P
[Old version datasheet]   60 Amp High-Performance Programmable ISR
logo
Micrel Semiconductor
SY89421V MICREL-SY89421V Datasheet
81Kb / 8P
   5V/3.3V HIGH-PERFORMANCE PHASE LOCKED LOOP
logo
Texas Instruments
PT6305 TI-PT6305 Datasheet
319Kb / 3P
[Old version datasheet]   3 AMP HIGH-PERFORMANCE ADJUSTABLE ISR
logo
Micrel Semiconductor
SY89423V MICREL-SY89423V Datasheet
98Kb / 8P
   5V/3.3V DUAL HIGH-PERFORMANCE PHASE LOCKED LOOP
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com