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AIS3624DQ Datasheet(PDF) 34 Page - STMicroelectronics |
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AIS3624DQ Datasheet(HTML) 34 Page - STMicroelectronics |
34 / 41 page Register description AIS3624DQ 34/41 DocID027117 Rev 2 7.18 INT2_SRC (35h) Interrupt 2 source register. Read-only register. Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT 2 pin) and allows the refresh of data in the INT2_SRC register if the latched option was chosen. 7.19 INT2_THS (36h) Table 48. Interrupt mode configuration AOI 6D Interrupt mode 0 0 OR combination of interrupt events 0 1 6-direction movement recognition 1 0 AND combination of interrupt events 1 1 6-direction position recognition Table 49. INT2_SRC register 0 IA ZH ZL YHYL XHXL Table 50. INT2_SRC description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) ZH Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) ZL Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) YH Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) YL Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) XH X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) XL X Low. Default value: 0 (0: no interrupt, 1: X low event has occurred) Table 51. INT2_THS register 0 THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 52. INT2_THS description THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000 |
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