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AIS3624DQ Datasheet(PDF) 18 Page - STMicroelectronics |
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AIS3624DQ Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 41 page  Digital interfaces AIS3624DQ 18/41 DocID027117 Rev 2 5 Digital interfaces The registers embedded inside the AIS3624DQ may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, the CS line must be tied high (i.e. connected to Vdd_IO). 5.1 I2C serial interface The AIS3624DQ I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the AIS3624DQ. When the bus is free, both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the normal mode. Table 8. Serial interface pin description Pin name Pin description CS SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) SCL SPC I2C serial clock (SCL) SPI serial port clock (SPC) SDA SDI SDO I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) SA0 SDO I2C less significant bit of the device address (SA0) SPI serial data output (SDO) Table 9. I2C terminology Term Description Transmitter The device which sends data to the bus Receiver The device which receives data from the bus Master The device which initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by the master |
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