CXK77P36E160GB / CXK77P18E160GB

Preliminary

16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1

4 / 25

March 2, 2001

Pin Description

Symbol

Type

Description

SA

Input

Synchronous Address Inputs - Registered on the rising edge of K.

DQa, DQb

DQc, DQd

I/O

Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations.

Driven from the falling edge of K during read operations.

DQa - indicates Data Byte a

DQb - indicates Data Byte b

DQc - indicates Data Byte c

DQd - indicates Data Byte d

K, K

Input

Differential Input Clocks

SS

Input

Synchronous Select Input - Registered on the rising edge of K.

SS = 0

specifies a write operation when SW = 0

specifies a read operation when SW = 1

SS = 1

specifies a deselect operation

SW

Input

Synchronous Global Write Enable Input - Registered on the rising edge of K.

SW = 0

specifies a write operation when SS = 0

SW = 1

specifies a read operation when SS = 0

SBWa, SBWb,

SBWc, SBWd

Input

Synchronous Byte Write Enable Inputs - Registered on the rising edge of K.

SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0

SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0

SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0

SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0

G

Input

Asynchronous Output Enable Input - Not supported. This control pin must be tied “low”.

ZZ

Input

Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode.

M1

Input

Read Operation Protocol Select 1 - This mode pin must be tied “high” to select Register - Latch

read operations.

M2

Input

Read Operation Protocol Select 2 - This mode pin must be tied “high” or “low”.

M2 = 0

selects Error-Correcting 8Mb R-L functionality

M2 = 1

selects conventional 16Mb R-L functionality

ZQ

Input

Output Impedance Control Resistor Input

3.3V Core Power Supply - Core supply voltage.

Output Power Supply - Output buffer supply voltage.

Input Reference Voltage - Input buffer threshold voltage.

Ground

TCK

Input

JTAG Clock

TMS

Input

JTAG Mode Select

TDI

Input

JTAG Data In

TDO

Output

JTAG Data Out

RSVD

Reserved - This pin is used for Sony test purposes only. It must be left unconnected.

NC

No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these