CXK77P36E160GB / CXK77P18E160GB

Preliminary

16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1

2 / 25

March 2, 2001

512K x 36 Pin Assignment (Top View)

Notes:

1. Pad Locations 2T and 6T are true no-connects. However, they are defined as SA address inputs in x18 LW SRAMs.

2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.

3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device.

4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied

“high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions

as an Error-Correcting 8Mb R-L SRAM.

5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional

SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”.

6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device.

1

2

3

4

5

6

7

A

SA

SA

NC

SA

SA

B

NC

SA

(5)

SA

NC

SA

SA

NC

C

NC

SA

SA

SA

SA

NC

D

DQc

DQc

ZQ

DQb

DQb

E

DQc

DQc

SS

DQb

DQb

F

DQc

DQb

G

DQc

DQc

SBWc

NC

SBWb

DQb

DQb

H

DQc

DQc

NC

DQb

DQb

J

K

DQd

DQd

K

DQa

DQa

L

DQd

DQd

SBWd

K

SBWa

DQa

DQa

M

DQd

SW

DQa

N

DQd

DQd

SA

DQa

DQa

P

DQd

DQd

SA

DQa

DQa

R

NC

SA

SA

NC

T

NC

NC

(1)

SA

SA

SA

NC

(1)

ZZ

U

TMS

TDI

TCK

TDO

RSVD

(2)