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ATMEGA16-16MC Datasheet(PDF) 73 Page - ATMEL Corporation

Part No. ATMEGA16-16MC
Description  8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash
Download  315 Pages
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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ATMEGA16-16MC Datasheet(HTML) 73 Page - ATMEL Corporation

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73
ATmega16(L)
2466E–AVR–10/02
quency of f
OC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is
defined by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM
option by its single-slope operation. The counter counts from BOTTOM to MAX then
restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOT-
TOM. In inverting Compare Output mode, the output is set on compare match and
cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the
fast PWM mode can be twice as high as the phase correct PWM mode that use dual-
slope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in Figure 32. The TCNT0 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent compare matches between OCR0 and TCNT0.
Figure 32. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If
the interrupt is enabled, the interrupt handler routine can be used for updating the com-
pare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0
pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM01:0 to 3 (See Table 40 on page 78).
The actual OC0 value will only be visible on the port pin if the data direction for the port
f
OC n
f
clk_I/O
2 N
1
OCRn
+
()
⋅⋅
-----------------------------------------------
=
TCNTn
OCRn Update and
TOVn Interrupt Flag Set
1
Period
2
3
OCn
OCn
(COMn1:0 = 2)
(COMn1:0 = 3)
OCRn Interrupt Flag Set
4
5
6
7


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