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ATMEGA16-16MC Datasheet(PDF) 49 Page - ATMEL Corporation

Part No. ATMEGA16-16MC
Description  8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash
Download  315 Pages
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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ATMEGA16-16MC Datasheet(HTML) 49 Page - ATMEL Corporation

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49
ATmega16(L)
2466E–AVR–10/02
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 20 summarizes the control signals for the pin value.
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 23, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
24 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
pd,max and tpd,min
respectively.
Figure 24. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the
Table 20. Port Pin Configurations
DDxn
PORTxn
PUD
(in SFIOR)
I/O
Pull-up
Comment
0
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled
low.
0
1
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
1
X
Output
No
Output High (Source)
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
in r17, PINx
0xFF
0x00
tpd, max
XXX
XXX
tpd, min


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