Reprogrammable CMOS
PAL® Device
PALC22V10
This is an abbreviated data sheet. Contact a Cypress
representative for complete specifications.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-03052 Rev. *A
Revised April 9, 2004
Features
• Advanced second-generation PAL® architecture
•Low power
— 55 mA max. “L”
— 90 mA max. standard
— 120 mA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
— 2 x (8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or
combinatorial operation
• 20, 25, 35 ns commercial and industrial
• 25, 30, 40 ns military
• Up to 22 input terms and 10 outputs
• High reliability
— Proven EPROM technology
— 100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, and PLCC
available
Functional Description
The Cypress PALC22V10 is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a
new concept, the “programmable macrocell.”
Logic Block Diagram (PDIP/CDIP)
Pin Configuration
LCC/PLCC
Top View
Macrocell
8
10
12
14
16
16
14
12
10
8
11
10
98
7
6
5
4
32
1
12
13
14
15
16
17
18
19
20
21
22
23
24
Preset
PROGRAMMABLE
AND ARRAY
(132 X 44)
I
I
II
I
I
I
III
CP/I
VSS
II/O9
I/O8
I/O 7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
1
NC
NC
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