NCP4206 datasheet(10/32 Pages) ONSEMI

Part #	NCP4206

Description	Digital Programmable Multi-Phase Synchronous Buck Converter

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NCP4206

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10

39

VCC

10kΩ

1V

NCP4206

680Ω

12V

DVFB =FBDV = 80mV – FBDV =0mV

+

–

16

COMP

15

FB

17

CSREF

7

GND

VID

DAC

32

31

VCC

Figure 5. Current Sensing Amplifier VOS

CSSUM

19

CSCOMP

18

39

VCC

CSREF

17

GND

7

39kΩ

680Ω

100nF

1kΩ

1V

NCP4206

VOS =

CSCOMP – 1V

40

12V

32

31

VCC

Figure 6. Positioning Voltage

Theory of Operation

The NCP4206 is a 6 phase VR11 controller; it combines

a multi−mode, fixed frequency PWM control with

multi−phase logic outputs for use in multi−phase

synchronous buck CPU core supply power converters. In

addition, the NCP4206 incorporates a serial interface to

allow the programming of key system performance

specifications and read back CPU data such as voltage,

current and power. Multiphase operation is important for

producing the high currents and low voltages demanded by

today’s microprocessors. Handling the high currents in a

single−phase converter would place high thermal demands

on the components in the system such as the inductors and

MOSFETs.

Start− Up Sequence

The NCP4206 follows the VR11 start−up sequence shown

in Figure 7. After both the EN and UVLO conditions are

met, a programmable internal timer goes through one cycle

TD1. This delay cycle is programmed using Delay

Command, default delay = 2 ms). The first eight clock

cycles of TD2 are blanked from the PWM outputs and used

for phase detection as explained in the following section.

Then the programmable internal soft−start ramp is enabled

(TD2) and the output comes up to the boot voltage of 1.1 V.

The boot hold time is also set by the Delay Command. This

second delay cycle is called TD3. During TD3 the processor

VID pins settle to the required VID code. When TD3 is over,

the NCP4206 reads the VID inputs and soft starts either up

or down to the final VID voltage (TD4). After TD4 has been

completed and the PWRGD masking time (equal to VID on

the fly masking) is finished, a third cycle of the internal timer

sets the PWRGD blanking (TD5).

The internal delay and soft start times are programmable

using the serial interface and the Delay Command and Soft

Start Command.

Figure 7. System Startup Sequence for VR11

TD1

5.0 V

SUPPLY

VTT I/O

(NCP4206 EN)

VCC_CORE

VR READY

(NCP4206 PWRGD)

CPU

VID INPUTS

VBOOT

V VID

UVLO

THRESHOLD

0.85 V

TD5

(1.1 V)

VID INVALID

TD4

TD2

TD3

VID VALID

50 ms

Soft Start

The Soft Start slope for the output voltage is set by an

internal timer. The default value is 0.5 V/msec, which can be

programmed through the SMBus interface. After TD1 and

the phase detection cycle have been completed, the SS time

(TD2 in Figure 5) starts. The SS circuit uses the internal VID

DAC to increase the output voltage in 6.25 mV steps up to

the 1.1 V boot voltage.

Once the SS circuit has reached the boot voltage, the boot

voltage delay time (TD3) is started. The end of the boot

voltage delay time signals the beginning of the second soft

start time (TD4). The SS voltage changes from the boot

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