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NCP308SNADJT1G Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP308SNADJT1G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 11 page NCP308, NCV308 www.onsemi.com 8 NCP308XX330 SENSE CT GND VDD NCP308XX120 SENSE CT GND VDD 3.3 V DSP/ RESET 1.2 V Figure 13. Using MR to Monitor Multiple System Voltages MR RESET Processor MR RESET Setting Reset Delay Time The NCP308 has three options for setting the reset delay time as shown in Table 5. Figure 14 shows the configuration for a fixed 300 ms typical delay time by tying CT to VDD; a resistor from 40 k W to 200 kW must be used. Figure 15 shows a fixed 20 ms delay time by leaving the CT pin unconnected. Figure 16 shows a user−defined program time between 1.25 ms and 10 s by connecting a capacitor between CT pin and ground. 3.3 V MR Rpullup SENSE CT GND VDD 50k Figure 14. Delay Time Fixed to 300 ms when CT Connected to VDD by Resistor MR RESET 3.3V MR Rpullup SENSE CT GND VDD Figure 15. Delay Time Fixed to 20 ms when CT is Open MR RESET 3.3 V MR Rpullup SENSE CT GND VDD CT Figure 16. Delay Time Set by Capacitor MR RESET The capacitor CT should be ≥ 100 pF for NCP308 to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using the following equation: |
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